Hardware Modeler Simulation Acceleration

A correction to the hardware modeler post is that simulation acceleration is not very likely using a hardware modeler.  In fact the simulations will most likely take much longer than regular RTL simulations.  It might be possible to achieve acceleration, but doing so would require carefully constructing the simulation with the test bench synthesized into the FPGA on the hardware modeler and limiting the amount of data transferred between the simulation software and the hardware modeler.  In this case, the hardware modeler would simply be an interface to a hardware accelerator (ie the FPGA).  There are hardware simulation accelerators available from Cadence based on this concept.