More Recent Communication Bus Statistics
The following table contains some statistics about digital communication busses that I have recently seen in designs, notably the bus length to bit period statistic that I have talked about in the past (the higher the bus length to bit period ratio, the more complex the design of the bus is).
| Example 1 | Example 2 | Example 3 | |
| Communication Standard | DDR 2 SDRAM | PCI-Express Cable Interface | DDR 2 SDRAM |
| Signaling Type | 1.8 V SSTL | Differential CML | 1.8 V SSTL |
| Communication Architecture | Hybrid Source Synchronous | Serial | Hybrid Source Synchronous |
| Bus Delay (ns) | 0.34 | 14.21 | 0.7 |
| Signaling Rate (Mbps) | 400 | 2500 | 533.33 |
| Data Rate (Mbps) | 400 | 2000 | 533.33 |
| Bit Error Rate | NA | 1.0 e-12 | NA |
| Ratio of bus length to bit period | 0.14 | 28.42 | 0.37 |
| Ratio of rise time to signaling bit period | 0.042 | 0.125 | 0.213 |
| Design Difficulty | 4 | 3 | 5 |
| Comments | Single SDRAM chip on board | Single DIMM (rank 1) on board - very narrow design space |
The design difficulty ratings are described as follows:
1 - very easy (no routing rules needed, just hook it up)
2 - easy (limited routing rules based on rules of thumb and app notes)
3 - average (routing rules needed based on rules of thumb, app notes, or SI simulation)
4 - difficult (routing rules developed with extensive SI simulation and modeling)
5 - very difficult (routing rules developed with extensive SI simulation and modeling, plus a very narrow solution space or a lot of difficulty getting it to work)
I have noticed a couple of things about DDR 2 SDRAM in the last couple of design examples I've worked on.
- There is plenty of design margin for interfaces with a single chip on the board for the data and data strobe signals
- Slew rates for single load designs are very high (off of the slew rate derating table) so you need to just use the worst case slew rate derating number from the table in your timing analysis
- Design margins are very tight for even a single DIMM case because of large length and delay variations on the DIMM at trace model corners