PID Control in an FPGA
I am working on an application that requires PID control. The design is an enhancement of a design that already has PID control implemented in a processor. There is already an FPGA in the design that provides glue logic and IO expansion for the processor including to the A/D and D/A converters in the control loop. The current processor does not have the power to implement the enhanced PID control. The idea is to use the FPGA to implement the PID controller. I have never used or seen an FPGA used in this type of DSP application before. Obviously the hardware design could be modified to include another DSP processor to implement this functionality, but would it be possible to use the existing FPGA. So I have done some research on this.
First I found an application note from Actel that describes how to implement an PID controller in programmable logic [1].
I found an academic paper describing an implementation of a PID controller in an FPGA although it includes no FPGA design architecture or HDL source code [2].
I found VHDL source code for a PID controller block posted in a forum at EDA Board. You do have to register on the site to get access to the attachment.
A mathematical model of a PID controller in verilog can be found at EDA.org. It is not synthesizable code, but it would be a starting point to modeling for HDL simualtion.
I found a general reference to digital PID controller design at www.ipendulum.com that might be adaptable to implementation in programmable logic instead of software.
I checked with the major FPGA vendors web sites (Xilinx, Altera, Lattice) and did not find any IP blocks available for implementing a PID controller. In general DSP related IP blocks for FPGAs tend to be audio or video filtering or compression, error correction coding, and generic filtering. I have not seen or heard of control loop based designs. Part of the reason is that digital control loops are fairly easy to implement in software, and DSP or processors chips have the horse power to handle them. I expect that it would probably take longer to implement the same control loop in an FPGA with a loss in flexibility for tweaking and calibration. There are definitely some applications where it makes sense though, so I'm a little surprised not to see any cores available. One thing I was not able to determine yet is how much FPGA resources a PID controller would take. Some further investigation and HDL coding / synthesizing will be necessary to get a good estimate.
Update - 10/7/2007
Since publishing this, my colleagues found another reference paper [3] that I would like to point out. This one does have some actual FPGA implementation details in it. It was a good starting point for designing the block.
[1] Actel Corporation. July 2007. "Application Note AC303: Implementing a PID Controller in an Actel FPGA." [Internet, WWW, PDF]. Available: Available in .PDF format; Address: http://www.actel.com/documents/PID_AN.pdf. [Accessed: 3-August-2009].
[2] Abdelati, Mohamed. "FPGA-Based PID Controller Implementation. The Islamic University of Gaza. Gaza Palestine. [Internet, WWW, PDF]. Available: Available in .PDF format; Address: http://www.iugaza.edu.ps/ara/research/articles/volume%2014-%20Issue%201%20-studies%20-7.pdf. [Accessed: 3-August-2009].
[3] Lima, Joao, Ricardo Menotti, Joao M. P. Cardoso, and Eduardo Marques. October 8-11, 2006. "A Methodology to Design FPGA-based PID Controllers." 2006 IEEE Internation Conference on Systems, Man, and Cybernetics. Taipei, Taiwan. Vol. 3, p 2577-2583.