Recent Communication Bus Statistics

The following table contains some statistics about digital communication busses that I have recently seen in designs, notably the bus length to bit period statistic that I have talked about in the past (the higher the bus length to bit period ratio, the more complex the design of the bus is). 

Communication Standard	Signaling Type	Communicaiton Architecture	Bus Delay (ns)	Signaling Rate (Mbps)	Data Rate (Mbps)	Bit Error Rate	Ratio of Bus Length to Data Bit Period	Ratio of Rise Time to Signaling Bit Period	Design Difficulty	Comment
Serial Rapid IO	Differential CML	Serial	4.8	3125	2500	1.00e-12	12	0.272	4
SATA	Differential CML	Serial	9.81	1500	1200	1.00e-12	11.77	0.410	4	Simulation performed using HSPICE buffer models
Digital LCD Interface	LVDS	Source Synchronous	9.1	378	378	NA	3.44	0.129	3
Digital LCD Interface	LVDS	Source Synchronous	12.3	571.4	571.4	NA	7.03	0.163	5	Timing margin was very negative largely because of potential cable skew
DDR II SDRAM	1.8 V SSTL	Hybrid Source Synchronous	0.714	667	667	NA	0.48	0.381	NA
CAN	Differential CAN	Serial	15.48	1	1	NA	0.02	0.025	2	Design did not have the right impedance cable, had a topology that was more like a hairball than a daisy chain, and did not have the termination resistors at the ends of the bus.  The design still worked fine.

The design difficulty ratings are described as follows:

1 - very easy (no routing rules needed, just hook it up)
2 - easy (limited routing rules based on rules of thumb and app notes)
3 - average (routing rules needed based on rules of thumb, app notes, or SI simulation)
4 - difficult (routing rules developed with extensive SI simulation and modeling)
5 - very difficult (routing rules developed with extensive SI simulation and modeling, plus a very narrow solution space or a lot of difficulty getting it to work)